The present invention relates to phase-locked loop circuits, and more particularly relates to technology for controlling the loop band width of a phase-locked loop circuit. A phase-locked loop circuit (which will be hereinafter also called a frequency synthesizer) is essential for an integrated circuit, and recent developments in radio communication have provided significant improvements in phase-locked loop circuits. Among others, a frequency synthesizer, in which sigma-delta modulation technique is applied to a frequency divider, (which will be hereinafter referred to as a “sigma-delta modulation frequency synthesizer”) has a large response time-constant, and is thus capable of responding quickly. In addition, sigma-delta modulation frequency synthesizers are capable of achieving very fine frequency resolution.
FIG. 11 illustrates the configuration of a sigma-delta modulation frequency synthesizer. Unlike a frequency divider in a typical phase-locked loop circuit, a frequency divider 50 (a dual modulus prescaler) in this sigma-delta modulation frequency synthesizer does not have a fixed frequency dividing ratio, and includes at least two frequency dividers (frequency dividers 51 and 52 in this example). When a sigma-delta modulator 100 uses the frequency dividers 51 and 52, the sigma-delta modulator 100 switches the frequency dividers 51 and 52 at a frequency higher than the loop band width. The oscillation frequency of the synthesizer is therefore determined by the use rates of the frequency dividers 51 and 52. For example, if the frequency divider 51, having a frequency dividing ratio of N+1, is used at a rate of 50%, and the frequency divider 52, having a frequency dividing ratio of N, is used at a rate of 50%, the oscillation frequency of the synthesizer is (N+½) times the frequency of input signal.
When the sigma-delta modulation frequency synthesizer switches the frequency dividers, switching noise is produced. However, by switching the frequency dividers at a high frequency and by performing sigma-delta modulation, the frequency components of the switching noise are centered in the high frequency region and removed by a loop filter 30, whereby the phase noise characteristics are improved. The frequency dividing ratio of the sigma-delta modulation frequency synthesizer is as low as about N, which allows the synthesizer to have a higher response frequency than a typical frequency synthesizer having a frequency dividing ratio of about the square of N.
In order to optimize the phase noise characteristics of a sigma-delta modulation frequency synthesizer, the loop band width thereof must be optimized. FIG. 12 is a graph indicating the switching noise characteristics of a sigma-delta modulation frequency synthesizer. The sigma-delta modulation frequency synthesizer's response shows low-pass filter characteristics to switching noise. Therefore, as the response frequency becomes lower, that is, the loop band width becomes lower, the switching noise is reduced further. FIG. 13 is a graph indicating the phase noise characteristics of the sigma-delta modulation frequency synthesizer. The sigma-delta modulation frequency synthesizer's response shows high-pass filter characteristics to VCO phase noise. Therefore, in order to reduce the VCO phase noise, the response frequency needs to be set high. As can be seen from the figures, since there is a trade-off between the switching noise and the VCO phase noise, the loop band width must be selected carefully so as to minimize the total amount of switching noise and VCO phase noise.
Nevertheless, so far there is no disclosed method for precisely optimizing the response characteristics of a phase-locked loop circuit, and there have only been techniques for partially controlling characteristics of a voltage controlled oscillator, etc. Under these circumstances, it might be difficult to enhance the performance of future sigma-delta modulation frequency synthesizers, etc.